1. Field of the Invention
The present invention relates to a semiconductor memory device having a burst access mode capable of high-speed read operation.
2. Description of the Background Art
In recent years, the progress of the process technique has improved the integration degree of a semiconductor memory device with an increased operating speed. Especially, the operating speed of the CPU (Central Processing Unit) has remarkably increased. In keeping with the operating speed of the CPU, therefore, the program data stored in the semiconductor memory device is required to be read at high speed. Demand is high, therefore, for an increased speed of the read operation of the semiconductor memory device.
Specifically, the music information and the image information such as animation have come to be stored in a single semiconductor chip. The music information can now be reproduced through the speaker or the image information can be reproduced on the display screen of a display unit. Variations in the speed of reading the music information or the image information would cause discontinuous music or image reproduction and give the sense of discomfort to the user.
The music information and the image information, therefore, are required to be read at high uniform speed. As a method to meet the requirement of high-speed access to the semiconductor memory device described above, the operation of the semiconductor memory device has come be performed in burst mode. Specifically, in burst mode, an address that is the base of the burst read operation of data, for example, is applied to the semiconductor device, and the data corresponding to each page are latched and read at a time. The addresses required for the burst read operation from the latch are generated continuously in the internal circuits and read sequentially. Accordingly, the address is not required to be read anew each time and a high-speed access can be achieved in reading a memory array.
For example, the memory cell data of 16 words of Nos. 0 to 15 are read, and while these 16-word data of numbers 0 to 15 are being output, the data of 16 words of Nos. 16 to 31 are read from the memory cell. This reading process is sequentially repeated. In this specification, one word is assumed to represent 16-bit data.
In the burst mode operation described above, each time one page has been read, the address of the next page is given to the semiconductor memory device anew. The decoding process of the input address in the next page readout should be carried out within the page readout time from the memory array by the sense amplifier.
Specifically, consider a case in which a given page is read with the start address for 15th data in the aforementioned example. The read time for only the 16th data can be secured. Therefore, no time margin can be secured for reading from the memory cell, thereby leading to the problem that it is difficult to output the data continuously.
In order to obviate this disadvantage, Japanese Patent Laying-Open No. 9-106689 discloses a method in which a sense amplifier and a latch circuit are arranged on each of the bit lines for reading the data of a memory array to eliminate the requirement of inputting a new address each time the page is switched. According to this method, the data are collectively read from all the bit lines and stored in a corresponding latch. A new address input is not required, therefore, at other than the time of switching the word line, thereby making high-speed read/write operation possible. In the system using the semiconductor memory device, therefore, the page read time is eliminated at the time of switching the page for an improved overall processing speed.
In the conventional semiconductor memory device described above, the fact that each bit line has a corresponding sense amplifier and a latch circuit for storing the data from the sense amplifier can shorten the access time can be shortened. Since the sense amplifiers and the latches occupy a large area of the chip, however, the disadvantage is encountered that the chip area is increased as compared with the ordinary semiconductor memory device.
Also, the provision of a sense amplifier for each bit line greatly increases the power consumption for reading the data. In an application to a battery-driven portable information device, therefore, the operating time of the portable information device is undesirably shortened.